Creating Symbols in Make file

So, let us make our file make file more nice ...

Now we will assign symbols, and some targets as well

mobi.mk

CC=gcc
OUT=mobi.exe
TARGET=main

build:
    $(CC)  $(TARGET).o -o $(OUT)

compile:
    $(CC) -c $(TARGET).c

clean:
    rm -f *.o $(OUT)

now try this nice command...

$ make -f ./mobi.mk clean compile build
rm -f *.o mobi.exe
gcc -c main.c
gcc  main.o -o mobi.exe

It is better to create a compilation of a module separate when working on it and compile that target only instead of compiling everything...

So, for so looks good...

Let's add the all target

mobi.mk

CC=gcc
OUT=mobi.exe
TARGET=main

all: clean compile build

build:
    $(CC)  $(TARGET).o -o $(OUT)

compile:
    $(CC) -c $(TARGET).c

clean:
    rm -f *.o $(OUT)

Now, we don't have to specify the targets...

$ make -f ./mobi.mk

rm -f *.o mobi.exe
gcc -c main.c
gcc  main.o -o mobi.exe